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| hyb25d512400/800/160at(l) 512-mbit double data rata sdram preliminary datasheet 2002-03-17 2002-03-17 page1of77 features double data rate architecture: two data transfers per clock cycle bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver dqs is edge-aligned with data for reads and is center-aligned with data for writes differential clock inputs (ck and ck ) four internal banks for concurrent operation data mask (dm) for write data dll aligns dq and dqs transitions with ck transitions commands entered on each positive ck edge; data and data mask referenced to both edges of dqs burst lengths: 2, 4, or 8 cas latency: (1.5), 2, 2.5, 3 auto precharge option for each burst access auto refresh and self refresh modes 7.8 s maximum average periodic refresh interval 2.5v (sstl_2 compatible) i/o v ddq =2.5v 0.2v v dd =2.5v 0.2v tsop66 package description the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. it is internally configured as a quad-bank dram. the 512mb ddr sdram uses a double-data-rate archi- tecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram effectively consists of a sin- gle 2n -bit wide, one clock cycle data transfer at the inter- nal dram core and two corresponding n-bit wide, one- half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr sdram during reads and by the memory controller during w rites. dqs is edge-aligned with data for reads and center-aligned with data for w rites. the 512mb ddr sdram operates from a differential clock (ck and ck ; the crossing of ck going h i gh and ck going lo w is referred to as the positive edge of ck). commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a pro- grammed sequence. accesses begin with the registration of an active command, which is then followed by a read or w rite command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coinci- dent with the read or w rite command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or w rite burst lengths of 2, 4 or 8 locations. an auto pre- charge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdrams, the pipelined, multibank archi- tecture of ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided along with a power-sav- ing power-down mode. all inputs are compatible with the je d e c standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timing specifi- cations included in this data sheet are for the dll e nabled mode of operation. cas latency and frequency cas latency maximum operating frequency (m hz ) ddr200 -8 ddr266a -7 ddr333 -6 2 100 133 133 2.5 125 143 166
hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 2 of 77 2002-03-03 pin configuration tsop66 1 2 3 4 5 6 9 10 11 12 13 14 7 8 15 16 17 18 19 20 21 22 66 65 64 63 62 61 58 57 56 55 54 53 60 59 52 51 50 49 48 47 46 45 23 24 25 44 43 42 26 27 41 40 28 29 30 31 32 33 39 38 37 36 35 34 v dd dq0 v ddq n c dq1 v ssq v ddq n c dq3 v ssq n c n c n c dq2 v ddq n c n c v dd n c n c we cas ras cs n c ba0 ba1 v ss dq7 v ssq n c dq6 v ddq v ssq n c dq4 v ddq n c n c n c dq5 v ssq dqs n c v r e f v ss dm ck ck ck e n c a12 a11 a9 v dd n c v ddq n c dq0 v ssq v ddq n c dq1 v ssq n c n c n c n c v ddq n c n c v dd n c n c we cas ras cs n c ba0 ba1 v ss n c v ssq n c dq3 v ddq v ssq n c dq2 v ddq n c n c n c n c v ssq dqs n c v r e f v ss dm ck ck ck e n c a12 a11 a9 a10/ap a0 a1 a2 a3 v dd a10/ap a0 a1 a2 a3 v dd a8 a7 a6 a5 a4 v ss a8 a7 a6 a5 a4 v ss 128mb x 4 64mb x 8 v dd dq0 v ddq dq1 dq2 v ssq v ddq dq5 dq6 v ssq dq7 n c dq3 dq4 v ddq ldqs n c v dd n c ldm we cas ras cs n c ba0 ba1 a10/ap a0 a1 a2 a3 v dd 32mb x 16 v ss dq15 v ssq dq14 dq13 v ddq v ssq dq10 dq9 v ddq dq8 n c dq12 dq11 v ssq u dqs n c v r e f v ss u dm ck ck ck e n c a12 a11 a9 a8 a7 a6 a5 a4 v ss hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 3 of 77 2002-03-03 input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sam- pled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). ck e input clock enable: ck eh i gh activates, and ck e low deactivates, internal clock signals and device input buffers and output drivers. taking ck e low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). ck e is synchronous for power down entry and exit, and for self refresh entry. ck e is asyn- chronous for self refresh exit. ck e must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and ck e are disabled during power-down. input buffers, excluding ck e , are disabled during self refresh. cs input chip select: all commands are masked when cs is registered h i gh .cs provides for exter- nal bank selection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. ras ,cas , we input command inputs: ras ,cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled h i gh coincident with that input data during a w rite access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, w rite or pre- charge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or e mrs cycle. a0 - a12 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/ w rite commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 lo w )orallbanks(a10 h i gh ). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode register set command. dq input/output data input/output: data bus. dqs input/output data strobe: output with read data, input with write data. e dge-aligned with read data, cen- tered in write data. u sedtocapturewritedata. n c no connect: n o internal electrical connection is present. v ddq supply dq power supply: 2.5v 0.2v. v ssq supply dq ground v dd supply power supply: 2.5v 0.2v. v ss supply ground v r e f supply sstl_2 reference voltage: (v ddq /2) hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 4 of 77 2002-03-03 ordering information part n umber (i n f) cas latency clock (m hz ) cas latency clock (m hz ) speed org. package hy b25d512400at(l)-8 * ) 2.5 125 2 100 ddr200 x4 66 pin tsop-ii hy b25d512800at(l)-8 x8 hy b25d512160at(l)-8 x16 hy b25d512400at(l)-7 143 133 ddr266a x4 hy b25d512800at(l)-7 x8 hy b25d512160at(l)-7 x16 hy b25d512400at(l)-6 166 133 ddr333 x4 hy b25d512800at(l)-6 x8 hy b25d512160at(l)-6 x16 * ) low power versions have a ?l? in the partnumber, f.e. hy b25d512400atl-8. these components are specifically selected for low idd6 self refresh currents. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 5 of 77 2002-03-03 block diagram (128mbit x 4) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 12 command decode a0-a12, ba0, ba1 ck e 13 15 i/o g ating dm mask logic bank0 memory array (8192 x 2048 x 8) sense amplifiers bank1 bank2 bank3 13 11 1 2 2 refresh counter 4 4 4 input register 1 1 1 1 1 8 8 2 8 clk out data mask data ck, col0 col0 col0 clk in m ux dqs g enerator 4 4 4 4 4 8 dq0-dq3, dm dqs 1 read latch w rite fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 2048 (x8) row-address m ux registers 13 bank0 row-address latch & decoder 8192 address register drivers bank control logic ck 15 16384 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 6 of 77 2002-03-03 block diagram (64mbit x 8) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 11 command decode a0-a12, ba0, ba1 ck e 15 i/o g ating dm mask logic bank0 memory array (8192 x 1024 x 16) sense amplifiers bank1 bank2 bank3 13 10 1 2 2 refresh counter 8 8 8 input register 1 1 1 1 1 16 16 2 16 clk out data mask data ck, col0 col0 col0 clk in m ux dqs g enerator 8 8 8 8 8 16 dq0-dq7, dm dqs 1 read latch w rite fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: dm is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional dq and dqs signals. column decoder 1024 (x16) row-address m ux registers 13 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck 15 16384 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 7 of 77 2002-03-03 block diagram (32mbit x 16) receivers 1 dqs ck, ck dll ras cas ck cs we ck control logic column-address counter/latch mode 10 command decode a0-a12, ba0, ba1 ck e 15 i/o g ating dm mask logic bank0 memory array (8192 x 512x 32) sense amplifiers bank1 bank2 bank3 13 9 1 2 2 refresh counter 16 16 16 input register 1 1 1 1 1 32 32 2 32 clk out data mask data ck, col0 col0 col0 clk in m ux dqs g enerator 16 16 16 16 16 32 dq0-dq15, dm ldqs, u dqs 2 read latch w rite fifo & drivers note: this functional block diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. note: u dm and ldm are unidirectional signals (input only), but is internally loaded to match the load of the bidirectional dq , u dqs and ldqs signals. column decoder 512 (x32) row-address m ux registers 13 16384 bank0 row-address latch & decoder 8192 address register drivers bank control logic 13 ck 15 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 8 of 77 2002-03-03 functional description the 512mb ddr sdram is a high-speed cmos, dynamic random-access memory containing 536,870,912 bits. the 512mb ddr sdram is internally configured as a quad-bank dram. the 512mb ddr sdram uses a double-data-rate architecture to achieve high-speed operation. the double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 512mb ddr sdram consists of a single 2n -bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half clock cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then followed by a read or w rite command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0-a12 select the row). the address bits registered coincident with the read or w rite com- mand are used to select the starting column location for the burst access. prior to normal operation, the ddr sdram must be initiali z ed. the following sections provide detailed infor- mation covering device initiali z ation, register definition, command descriptions and device operation. initialization ddr sdrams must be powered up and initiali z ed in a predefined manner. operational procedures other than those specified may result in undefined operation. the following criteria must be met: n o power sequencing is specified during power up or power down given the following criteria: v dd and v ddq are driven from a single power converter output v tt meets the specification a minimum resistance of 42 ohms limits the input current from the v tt supply into any pin and v ref tracks v ddq /2 or the following relationship must be followed: v ddq is driven after or with v dd such that v ddq hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 10 of 77 2002-03-03 mode register operation a8 a7 a6 a5 a4 cas latency a3 a2 a1 a0 burst length bt address bus cas latency a6 a5 a4 latency 000 reserved 001 reserved 010 2 011 3 100 reserved 1 0 1 1.5 (optional) 110 2.5 111 reserved burst length a2 a1 a0 burst length 000 reserved 001 2 010 4 011 8 100 reserved 101 reserved 110 reserved 111 reserved ba1 ba0 a11 a10 a9 0 * 0 * mode register operating mode * ba0andba1mustbe0,0toselectthemoderegister (vs. the e xtended mode register). a12 - a9 a8 a7 a6 - a0 operating mode 000valid n ormal operation do not reset dll 010valid n ormal operation in dll reset 001 testmode ??? reserved a3 burst type 0 sequential 1 interleave a12 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 11 of 77 2002-03-03 notes: 1. for a burst length of two, a1-ai selects the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai selects the four-data-element block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- element block; a0-a2 selects the first access within the block. 4. w henever a boundary of the block is reached within a given sequence above, the following access wraps within the block. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definition on page 11. read latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2, 2.5 and 3 clocks. cas latency of 1.5 is an optional feature on this device. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n+ m. reserved states should not be used as unknown operation or incompatibility with future versions may result. burst definition burst length starting column address order of accesses w ithin a burst a2 a1 a0 type = sequential type = interleaved 2 00-1 0-1 11-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 12 of 77 2002-03-03 operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a12 set to z ero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set com- mand with bits a7 and a9-a12 each set to z ero, bit a8 set to one, and bits a0-a6 set to the desired values. a mode register set command issued to reset the dll should always be followed by a mode register set command to select normal operating mode. all other combinations of values for a7-a12 are reserved for future use and/or test modes. test modes and reserved states should not be used as unknown operation or incompatibility with future versions may result. required cas latencies n op n op n op n op n op read cas latency = 2, bl = 4 shown with nominal t ac ,t dqsck ,andt dqsq . ck ck command dqs dq don?t care cl=2 n op n op n op n op n op read cas latency = 2.5, bl = 4 ck ck command dqs dq cl=2.5 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 13 of 77 2002-03-03 extended mode register the e xtended mode register controls functions beyond those controlled by the mode register; these addi- tional functions include dll enable/disable, and output drive strength selection (optional). these functions are controlled via the bits shown in the e xtended mode register definition. the e xtended mode register is programmed via the mode register set command (with ba0 = 1 and ba1 = 0) and retains the stored informa- tion until it is programmed again or the device loses power. the e xtended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent oper- ation. violating either of these requirements result in unspecified operation. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power up initiali z ation, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. this is the reason 200 clock cycles must occur before issuing a read or w rite command upon exit of self refresh operation. output drive strength the normal drive strength for all outputs is specified to be sstl_2, class ii. in addition this design version supports a weak driver mode for lighter load and/or point-to-point environments which can be activated during mode register set. i-v curves for the normal and weak drive strength are included in this document. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 14 of 77 2002-03-03 extended mode register definition a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 * address bus drive strength a 1 drive strength 0 n ormal 1 w eak ba1 ba0 operating mode a 11 a 10 a 9 0 * 1 * * ba0 and ba1 must be 1, 0 to select the e xtended mode register mode register e xtended ds dll a 0 dll 0 e nable 1 disable an - a3 a2 - a0 operating mode 0valid n ormal operation ?? all other states reserved (vs.thebasemoderegister) a 12 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 15 of 77 2002-03-03 commands deselect the deselect function prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the n ooperation( n op) command is used to perform a n op to a ddr sdram. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode registers are loaded via inputs a0-a12, ba0 and ba1. see mode register descriptions in the reg- ister definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge (or read or w rite with auto precharge) is issued to that bank. a precharge (or read or w rite with auto precharge) command must be issued and com- pleted before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, a j (where [ i=8, j = don?t care ] for x16, [ i=9, j = don?t care ] for x8 and [ i=9, j =11 ] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the read burst; if auto precharge is not selected, the row remains open for subsequent accesses. write the w rite command is used to initiate a burst write access to an active (open) row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-ai, a j (where [ i=9, j =don?tcare ] for x8; where [ i=9, j =11 ] for x4) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed is precharged at the end of the w rite burst; if auto precharge is not selected, the row remains open for subsequent accesses. input data appearing on the dqs is written to the memory array sub j ect to the dm input logic level appearing coin- cident with the data. if a given dm signal is registered low, the corresponding data is written to memory; if the dm signal is registered high, the corresponding data inputs are ignored, and a w rite is not executed to that byte/column location. precharge the precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 16 of 77 2002-03-03 as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or w rite commands being issued to that bank. a precharge command is treated as a n op if there is no open row in that bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in con j unction with a specific read or w rite command. a precharge of the bank/row that is addressed with the read or w rite command is automatically performed upon completion of the read or w rite burst. auto pre- charge is nonpersistent in that it is either enabled or disabled for each individual read or w rite command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most re- cently registered read command prior to the burst terminate command is truncated, as shown in the opera- tion section of this data sheet. auto refresh auto refresh is used during normal operation of the ddr sdram and is analogous to cas before ras (cbr) refresh in previous dram types. this command is nonpersistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 512mb ddr sdram requires auto refresh cycles at an aver- age periodic interval of 7.8 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted in the system, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 * 7.8 s (70.2 s). this maximum absolute interval is short enough to allow for dll updates internal to the ddr sdram to be restricted to auto refresh cycles, without allowing too much drift in t ac between updates. self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. w hen in the self refresh mode, the ddr sdram retains data without external clocking. the self refresh command is initiated as an auto refresh command coincident with ck e transitioning low. the dll is automatically disabled upon entering self refresh, and is automatically enabled upon exiting self refresh (200 clock cycles must then occur before a read command can be issued). input signals except ck e (low) are ?don?t care? during self refresh operation. the procedure for exiting self refresh requires a sequence of commands. ck (and ck ) must be stable prior to ck e returning high. once ck e is high, the sdram must have n op commands issued for t x s n r because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll requirements is to apply n ops for 200 clock cycles before applying any other command. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 17 of 77 2002-03-03 truth table 1a: commands n ame (function) cs ras cas we address m ne n otes deselect ( n op) hxxx x n op 1, 9 n ooperation( n op) l hhh x n op 1, 9 active (select bank and activate row) l l hh bank/row act 1, 3 read (select bank and column, and start read burst) l h l h bank/col read 1, 4 w rite (select bank and column, and start w rite burst) l h ll bank/col w rite 1, 4 burst terminate l hh l x bst 1, 8 precharge (deactivate row in bank or banks) l l h lcode pr e 1, 5 auto refresh or self refresh ( e nter self refresh mode) l l l hx ar/sr 1,6,7 mode register set l l l l op-code mrs 1, 2 1. ck e is h i gh for all commands shown except self refresh. 2. ba0, ba1 select either the base or the e xtended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects e xtended mode register; other combinations of ba0-ba1 are reserved; a0-a12 provide the op-code to be written to the selected mode register.) 3. ba0-ba1 provide bank address and a0-a12 provide row address. 4. ba0, ba1 provide bank address; a0-a i provide column address (where i =8forx16, i = 9 for x8 and 9, 11 for x4); a10 h i gh enables the auto precharge feature (nonpersistent), a10 lo w disables the auto precharge feature. 5. a10 lo w : ba0, ba1 determine which bank is precharged. a10 h i gh : all banks are precharged and ba0, ba1 are ?don?t care.? 6. this command is a u to r e fr e s h if ck e is h i gh ;selfrefreshifck e is lo w . 7. internal refresh counter controls row and bank addressing; all inputs and i/os are ?don?t care? except for ck e . 8. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled or for write bursts 9. deselect and n op are functionally interchangeable. truth table 1b: dm operation n ame (function) dm dqs n otes w rite e nable l valid 1 w rite inhibit hx 1 1. u sed to mask write data; provided coincident with the corresponding data. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 18 of 77 2002-03-03 operations bank/row activation before any read or w rite commands can be issued to a bank within the ddr sdram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0-a12, ba0 and ba1 (see activating a specific row in a specific bank), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or w rite command may be issued to that row, sub j ect to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active com- mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . activatingaspecificrowinaspecificbank ra ba h i gh ra = row address. ba = bank address. ck ck ck e cs ras cas we a0-a12 ba0, ba1 don?t care hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 19 of 77 2002-03-03 reads subsequent to programming the mode register with cas latency, burst type, and burst length, read bursts are initiated with a read command, as shown on read command on page 20. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row that is accessed starts pre- charge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. e ach subsequent data-out element is valid nominally at the next posi- tive or negative clock edge (i.e. at the next crossing of ck and ck ). read burst: cas latencies (burst length =4) on page 21 shows general timing for each supported cas latency setting. dqs is driven by the ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out element is known as the read postamble. u pon completion of a burst, assuming no other commands have been initiated, the dqs goes h igh- z . data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). this is shown on consecutive read bursts: cas latencies (burst length = 4 or 8) on page 22. a read command can be initiated on any clock cycle following a previous read command. n onconsecutive read data is illustrated on non-consecutive read bursts: cas latencies (burst length = 4) on page 23. full-speed random read accesses: cas latencies (burst length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 24. t rcd and t rrd definition ro w act n op col ro w ba y ba y ba x act n op n op ck ck command a0-a12 ba0, ba1 don?t care rd/ w r t rcd t rrd rd/ w r n op n op hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 20 of 77 2002-03-03 read command ba h i gh ca = column address ba = bank address ck e cs ras cas we a10 ba0, ba1 don?t care ca x4:a0-a9,a11 x8: a0-a9 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck x16: a0-a8 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 21 of 77 2002-03-03 read burst: cas latencies (burst length = 4) cas latency = 2 n op n op n op n op n op read ck ck command address dqs dq cas latency = 2.5 don?t care ba a,col n doa-n cl=2.5 n op n op n op n op n op read ck ck command address dqs dq ba a,col n doa-n do a-n = data out from bank a, column n. 3 subsequent elements of data out appear in the programmed order following do a-n. shownwithnominalt ac ,t dqsck ,andt dqsq . cl=2 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 22 of 77 2002-03-03 consecutive read bursts: cas latencies (burst length = 4 or 8) cas latency = 2 n op read n op n op n op read ck ck command address dqs dq cl=2 baa, col n baa, col b don?t care do a-n (or a-b) = data out from bank a, column n (or bank a, column b). w hen burst length = 4, the bursts are concatenated. w hen burst length = 8, the second burst interrupts the first. 3 subsequent elements of data out appear in the programmed order following do a-n. 3 (or 7) subsequent elements of data out appear in the programmed order following do a-b. shownwithnominalt ac ,t dqsck ,andt dqsq . cas latency = 2.5 n op read n op n op n op read ck ck command address dqs dq cl=2.5 baa, col n baa,col b doa-n doa- n doa- b doa-b hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 23 of 77 2002-03-03 non-consecutive read bursts: cas latencies (burst length = 4) cas latency = 2 n op n op read n op n op read ck ck command address dqs dq do a-n doa- b do a-n (or a-b) = data out from bank a, column n (or bank a, column b). 3 subsequent elements of data out appear in the programmed order following do a-n (and following do a-b). shownwithnominalt ac ,t dqsck ,andt dqsq . don?t care baa, col n baa, col b cl=2 cas latency = 2.5 n op n op read n op n op read do a-n doa- b baa, col n baa, col b cl=2.5 ck ck command address dqs dq n op hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 24 of 77 2002-03-03 random read accesses: cas latencies (burst length = 2, 4 or 8) doa-n cas latency = 2 read read read n op n op read doa-b doa-n ' doa-x doa-x ' doa-b? doa-g ck ck command address dqs dq do a-n, etc. = data out from bank a, column n etc. n ' etc. = odd or even complement of n, etc. (i.e., column address lsb inverted). reads are to active rows in any banks. shown with nominal t ac ,t dqsck ,andt dqsq . don?t care baa, col n baa, col x baa, col b baa, col g cl=2 doa-n cas latency = 2.5 read read read n op n op read doa-b doa-n ' doa-x doa-x ' doa-b? ck ck command address dqs dq baa, col n baa, col x baa, col b baa, col g cl=2.5 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 25 of 77 2002-03-03 data from any read burst may be truncated with a burst terminate command, as shown on terminating a read burst: cas latencies (burst length = 8) on page 26. the burst terminate latency is equal to the read (cas) latency, i.e. the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs. data from any read burst must be completed or truncated before a subsequent w rite command can be issued. if truncation is necessary, the burst terminate command must be used, as shown on read to write: cas latencies (burst length = 4 or 8) on page 27. the example is shown for t dqss (min). the t dqss (max) case, not shown here, has a longer bus idle time. t dqss (min) and t dqss (max) are defined in the section on w rites. a read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated). the precharge command should be issued x cycles after the read com- mand, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch archi- tecture). this is shown on read to precharge: cas latencies (burst length = 4 or 8) on page 28 for read latencies of 2 and 2.5. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. n ote that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto pre- charge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 26 of 77 2002-03-03 terminating a read burst: cas latencies (burst length = 8) cas latency = 2 n op bst n op n op n op read ck command address dqs dq do a-n = data out from bank a, column n. cases shown are bursts of 8 terminated after 4 data elements. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac ,t dqsck ,andt dqsq . doa-n don?t care ck baa, col n cl=2 cas latency = 2.5 n op bst n op n op n op read ck command address dqs dq doa-n ck baa, col n cl=2.5 n o further output data after this point. dqs tristated. n o further output data after this point. dqs tristated. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 27 of 77 2002-03-03 read to write: cas latencies (burst length = 4 or 8) cas latency = 2 bst n op w rite n op n op read di a-b ck ck command address dqs dq dm doa-n do a-n = data out from bank a, column n 1 subsequent elements of data out appear in the programmed order following do a-n. data in elements are applied following dl a-b in the programmed order, according to burst length. don?t care baa, col n baa, col b cl=2 t dqss (min) cas latency = 2.5 bst n op n op w rite n op read ck ck command address dqs dq dm doa-n baa, col n baa, col b cl=2.5 t dqss (min) dla-b shown with nominal t ac ,t dqsck ,andt dqsq . . di a-b = data in to bank a, column b hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 28 of 77 2002-03-03 read to precharge: cas latencies (burst length = 4 or 8) cas latency = 2 n op pr en op n op act read ck ck command address dqs dq doa-n do a-n = data out from bank a, column n. cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8. 3 subsequent elements of data out appear in the programmed order following do a-n. shown with nominal t ac ,t dqsck ,andt dqsq . don?t care baa,coln baaorall ba a, ro w cl=2.5 cas latency = 2.5 n op pr en op n op act read ck ck command address dqs dq doa-n t rp ba a, col n ba a or all ba a, ro w cl=2 t rp hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 29 of 77 2002-03-03 writes w rite bursts are initiated with a w rite command, as shown on write command on page 30. the starting column and bank addresses are provided with the w rite command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic w rite commands used in the following illustrations, auto pre- charge is disabled. during w rite bursts, the first valid data-in element is registered on the first rising edge of dqs following the write command, and subsequent data elements are registered on successive edges of dqs. the low state on dqs between the w rite command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the w rite com- mand and the first corresponding rising edge of dqs (t dqss ) is specified with a relatively wide range (from 75 % to 125 % of one clock cycle), so most of the w rite diagrams that follow are drawn for the two extreme cases (i.e. t dqss (min) and t dqss (max)). write burst (burst length = 4) on page 31 shows the two extremes of t dqss foraburstoffour. u pon completion of a burst, assuming no other commands have been initiated, the dqs and dqs enters h igh- z and any additional input data is ignored. data for any w rite burst may be concatenated with or truncated with a subsequent w rite command. in either case, a continuous flow of input data can be maintained. the new w rite command can be issued on any pos- itive edge of clock following the previous w rite command. the first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new w rite command should be issued x cycles after the first w rite command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). write to write (burst length = 4) on page 32 shows concatenated bursts of 4. an example of non-consecutive w rites is shown on write to write: max dqss, non-consecutive (burst length = 4) on page 33. full-speed random write accesses within a page or pages can be performed as shown on random write cycles (burst length = 2, 4 or 8) on page 34. data for any w rite burst may be followed by a subsequent read command. to follow a w rite without truncating the write burst, t w tr ( w rite to read) should be met as shown on write to read: non- interrupting (cas latency = 2; burst length = 4) on page 35. data for any w rite burst may be truncated by a subsequent read command, as shown in the figures on write to read: interrupting (cas latency = 2; burst length = 8) on page 36 to write to read: nominal dqss, inter- rupting (cas latency = 2; burst length = 8) on page 38. n ote that only the data-in pairs that are registered prior to the t w tr period are written to the internal array, and any subsequent data-in must be masked with dm, as shown in the diagrams noted previously. data for any w rite burst may be followed by a subsequent precharge command. to follow a w rite without truncating the write burst, t w r should be met as shown on write to precharge: non-interrupting (burst length =4) on page 39. data for any w rite burst may be truncated by a subsequent precharge command, as shown in the figures on write to precharge: interrupting (burst length = 4 or 8) on page 40 to write to precharge: nominal dqss (2 bit write), interrupting (burst length = 4 or 8) on page 42. n ote that only the data-in pairs that are registered prior to the t w r period are written to the internal array, and any subsequent data in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. inthecaseofa w rite burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same burst with auto pre- charge. the disadvantage of the precharge command is that it requires that the command and address bus- ses be available at the appropriate time to issue the command. the advantage of the precharge command is thatitcanbeusedtotruncatebursts. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 30 of 77 2002-03-03 write command ba h i gh ca = column address ba = bank address ck e cs ras cas we a10 ba0, ba1 don?t care ca x4:a0-a9,a11 x8: a0-a9 x16: a0-a8 en ap dis ap en ap = enable auto precharge dis ap = disable auto precharge ck ck hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 31 of 77 2002-03-03 write burst (burst length = 4) t1 t2 t3 t4 t dqss (max) n op n op n op w rite di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. a10 is low with the w rite command (auto precharge is disabled). ck ck command address dqs dq dm don?t care maximum dqss ba a, col b t1 t2 t3 t4 t dqss (min) n op n op n op w rite ck ck command address dqs minimum dqss ba a, col b dq dm dla-b dla-b hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 32 of 77 2002-03-03 write to write (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss n op w rite n op n op n op w rite di a-b = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. e ach w rite command may be to any bank. ck ck command address dqs dq dm don?t care t1 t2 t3 t4 t5 t6 minimum dqss n op w rite n op n op n op w rite ck ck command address dqs dq dm baa, col b baa, col n ba, col b ba, col n t dqss (min) di a-b di a-n di a-b di a-n hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 33 of 77 2002-03-03 write to write: max dqss, non-consecutive (burst length = 4) t1 t2 t3 t4 t5 t dqss (max) n op n op w rite n op w rite di a-b, etc. = data in for bank a, column b, etc. 3 subsequent elements of data in are applied in the programmed order following di a-b. 3 subsequent elements of data in are applied in the programmed order following di a-n. a non-interrupted burst is shown. e ach w rite command may be to any bank. ck ck command address dqs dq dm don?t care baa, col b baa, col n di a-b di a-n hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 34 of 77 2002-03-03 random write cycles (burst length = 2, 4 or 8) t1 t2 t3 t4 t5 t dqss (max) maximum dqss w rite w rite w rite w rite w rite di a-b di a-n di a-b, etc. = data in for bank a, column b, etc. b ' , etc. = odd or even complement of b, etc. (i.e., column address lsb inverted). e ach w rite command may be to any bank. di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm don?t care baa, col b baa, col x baa, col n baa, col a baa, col g t1 t2 t3 t4 t5 minimum dqss w rite w rite w rite w rite w rite di a-b di a-n di a-b? di a-x di a-x? di a-n? di a-a di a-a? ck ck command address dqs dq dm baa, col b baa, col x baa, col n baa, col a baa, col g t dqss (min) di a-g hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 35 of 77 2002-03-03 write to read: non-interrupting (cas latency = 2; burst length = 4) cl = 2 t1 t2 t3 t4 t5 t6 t w tr n op n op n op read w rite di a-b n op di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t w tr is referenced from the first positive ck edge after the last data in pair. a10 is low with the w rite command (auto precharge is disabled). the read and w rite commands may be to any bank. ck ck command address dqs dq dm don?t care maximum dqss baa, col b baa, col n t1 t2 t3 t4 t5 t6 t w tr n op n op n op read w rite n op ck ck command address minimum dqss baa, col b baa, col n t dqss (max) di a-b dqs dq dm t dqss (min) cl = 2 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 36 of 77 2002-03-03 write to read: interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (max) maximum dqss n op n op n op read w rite n op di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t w tr is referenced from the first positive ck edge after the last data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the w rite command (auto precharge is disabled). the read and w rite commands are not necessarily to the same bank. dia- b ck ck command address dqs dq dm don?t care baa, col b baa, col n t w tr cl = 2 t1 t2 t3 t4 t5 t6 minimum dqss n op n op n op read w rite n op ck ck command address baa, col b baa, col n t w tr di a-b dqs dq dm cl = 2 t dqss (min) 1 = these bits are incorrectly written into the memory array if dm is low. 11 11 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 37 of 77 2002-03-03 write to read: minimum dqss, odd number of data (3 bit write), interrupting (cas latency = 2; burst length = 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 3 data elements are written. 2 subsequent elements of data in are applied in the programmed order following di a-b. t w tr is referenced from the first positive ck edge after the last desired data in pair (not the last desired data in element) the read command masks the last 2 data elements in the burst. a10 is low with the w rite command (auto precharge is disabled). thereadand w rite commands are not necessarily to the same bank. don?t care t1 t2 t3 t4 t5 t6 n op n op n op read w rite n op ck ck command address baa, col b baa, col n t w tr di a-b dqs dq cl = 2 t dqss (min) dm 122 1 = this bit is correctly written into the memory array if dm is low. 2 = these bits are incorrectly written into the memory array if dm is low. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 38 of 77 2002-03-03 write to read: nominal dqss, interrupting (cas latency = 2; burst length = 8) t1 t2 t3 t4 t5 t6 t dqss (nom) n op n op n op read w rite n op di a-b = data in for bank a, column b. an interrupted burst is shown, 4 data elements are written. 3 subsequent elements of data in are applied in the programmed order following di a-b. t w tr is referenced from the first positive ck edge after the last desired data in pair. the read command masks the last 2 data elements in the burst. a10 is low with the w rite command (auto precharge is disabled). the read and w rite commands are not necessarily to the same bank. di a-b ck ck command address dqs dq dm don?t care baa, col b baa, col n t w tr cl = 2 1 = these bits are incorrectly written into the memory array if dm is low. 1 1 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 39 of 77 2002-03-03 write to precharge: non-interrupting (burst length = 4) t1 t2 t3 t4 t5 t6 t dqss (max) n op n op n op n op w rite di a-b pr e di a-b = data in for bank a, column b. 3 subsequent elements of data in are applied in the programmed order following di a-b. a non-interrupted burst is shown. t w r is referenced from the first positive ck edge after the last data in pair. a10 is low with the w rite command (auto precharge is disabled). ck ck command address dqs dq dm don?t care ba a, col b ba (a or all) t w r maximum dqss t1 t2 t3 t4 t5 t6 n op n op n op n op w rite pr e ck ck command address ba a, col b ba (a or all) t w r minimum dqss di a-b dqs dq dm t dqss (min) t rp t rp hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 40 of 77 2002-03-03 write to precharge: interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t w r is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst, for burst length = 8. a10 is low with the w rite command (auto precharge is disabled). 1=canbedon ' t care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don ' t care at this point. don?t care t1 t2 t3 t4 t5 t6 n op n op n op pr e w rite n op ck ck command address maximum dqss di a-b 11 2 dqs dq dm t dqss (max) t rp t1 t2 t3 t4 t5 t6 n op n op n op pr e w rite n op ck ck command address ba a, col b ba (a or all) minimum dqss t w r t rp di a-b 11 dqs dq dm t dqss (min) 2 ba a, col b ba (a or all) t w r 3=thesebitsareincorrectlywrittenintothememoryarrayifdmislow. 3 3 3 3 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 41 of 77 2002-03-03 write to precharge: minimum dqss, odd number of data (1 bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 1 data element is written. t w r is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the w rite command (auto precharge is disabled). 1=canbedon ' t care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don ' t care at this point. don?t care t1 t2 t3 t4 t5 t6 n op n op n op pr e w rite n op ck ck command address ba a, col b ba (a or all) t w r t rp di a-b dqs dq t dqss (min) 2 11 dm 344 3 = this bit is correctly written into the memory array if dm is low. 4=thesebitsareincorrectlywrittenintothememoryarrayifdmislow. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 42 of 77 2002-03-03 write to precharge: nominal dqss (2 bit write), interrupting (burst length = 4 or 8) di a-b = data in for bank a, column b. an interrupted burst is shown, 2 data elements are written. 1 subsequent element of data in is applied in the programmed order following di a-b. t w r is referenced from the first positive ck edge after the last desired data in pair. the precharge command masks the last 2 data elements in the burst. a10 is low with the w rite command (auto precharge is disabled). 1=canbedon ' t care for programmed burst length of 4. 2 = for programmed burst length of 4, dqs becomes don ' t care at this point. don?t care t1 t2 t3 t4 t5 t6 n op n op n op pr e w rite n op ck ck command address ba a, col b ba (a or all) t rp t dqss (nom) di a-b 1 2 dqs dq dm 1 t w r 3 3 3 = these bits are incorrectly written into the memory array if dm is low. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 43 of 77 2002-03-03 precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time (t rp ) after the precharge com- mand is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. w hen all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or w rite commands being issued to that bank. precharge command ba h i gh ba = bank address ck ck ck e cs ras cas we a10 ba0, ba1 don?t care all banks one bank (if a10 is low, otherwise don?t care). a0-a9, a11, a12 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 44 of 77 2002-03-03 power-down power-down is entered when ck e is registered lo w (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. e ntering power-down deactivates the input and output buffers, excluding ck, ck and ck e . the dll is still running in power down mode, so for maximum power savings, the user has the option of disabling the dll prior to entering power- down. in that case, the dll must be enabled after exiting power-down, and 200 clock cycles must occur before a read command can be issued. in power-down mode, ck e low and a stable clock signal must be maintained at the inputs of the ddr sdram, and all other input signals are ?don?t care?. h owever, power- down duration is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-down mode. the power-down state is synchronously exited when ck e is registered h i gh (along with a n op or deselect command). a valid, executable command may be applied one clock cycle later. power down t is t is ck ck ck e command n ocolumn access in progress valid n op valid don?t care e xit power down mode e nter power down mode (burst read or w rite operation must not be in progress) n op hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 45 of 77 2002-03-03 truth table 2: clock enable (cke) 1. ck e n is the logic state of ck e at clock edge n: ck e n-1wasthestateofck e at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. comma n d n is the command registered at clock edge n, and actio n nisaresultofcomma n dn. 4. all states and sequences not shown are illegal or reserved. current state ck e n-1 ck e n command n action n n otes previous cycle current cycle self refresh l l x maintain self-refresh self refresh l h deselect or n op e xit self-refresh 1 power down l l x maintain power-down power down l h deselect or n op e xit power-down all banks idle h l deselect or n op precharge power-down e ntry all banks idle h la u to r e fr e s h self refresh e ntry bank(s) active h l deselect or n op active power-down e ntry hh see ?truth table 3: current state bankn-commandtobankn (same bank)? on page 46 1. deselect or n op commands should be issued on any clock edges occurring during the self refresh e xit (t x s n r ) period. a mini- mum of 200 clock cycles are needed before applying a read command to allow the dll to lock to the input clock. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 46 of 77 2002-03-03 truth table 3: current state bank n - command to bank n (same bank) current state cs ras cas we command action n otes any hxxx deselect n op. continue previous operation 1-6 l hhh n o operation n op. continue previous operation 1-6 idle ll hh active select and activate row 1-6 lll h a u to r e fr e s h 1-7 llllmod e r eg ist e rs e t 1-7 row active l h l h read select column and start read burst 1-6, 10 l h ll w rite select column and start w rite burst 1-6, 10 ll h l precharge deactivate row in bank(s) 1-6, 8 read (auto precharge disabled) l h l h read select column and start new read burst 1-6, 10 ll h l precharge truncate read burst, start precharge 1-6, 8 l hh lb u rst t e rmi n at e b u rst t e rmi n at e 1-6, 9 w rite (auto precharge disabled) l h l h read select column and start read burst 1-6, 10, 11 l h ll w rite select column and start w rite burst 1-6, 10 ll h l precharge truncate w rite burst, start precharge 1-6, 8, 11 1. this table applies when ck e n-1 was h i gh and ck e nis h i gh (see truth table 2: clock e nable (ck e )andaftert x s n r/ t x srd has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. e xceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. n odatabursts/accessesandnoregister accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. w rite: a w rite burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp ismet,thebankisinthe idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd ismet,thebankisinthe ?row active? state. read w/auto precharge e nabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. w rite w/auto precharge e nabled: starts with registration of a w rite command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. deselect or n op commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to truth table 4. 5. the following states must not be interrupted by any executable command; deselect or n op commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the ddr sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks is in theidlestate. 6. all states and sequences not shown are illegal or reserved. 7. n ot bank-specific; requires that all banks are idle. 8. may or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 9. n ot bank-specific; b u rst t e rmi n at e affects the most recent read burst, regardless of bank. 10. reads or w rites listed in the command/action column include reads or w rites with auto precharge enabled and reads or w rites with auto precharge disabled. 11. requires appropriate dm masking. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 47 of 77 2002-03-03 truth table 4: current state bank n - command to bank m (different bank) current state cs ras cas we command action n otes any hxxx deselect n op/continue previous operation 1-6 l hhh n ooperation n op/continue previous operation 1-6 idle xxxx any command otherwise allowedtobankm 1-6 row activating, active, or precharging ll hh active select and activate row 1-6 l h l h read select column and start read burst 1-7 l h ll w rite select column and start w rite burst 1-7 ll h l precharge 1-6 read (auto precharge disabled) ll hh active select and activate row 1-6 l h l h read select column and start new read burst 1-7 ll h l precharge 1-6 w rite (auto precharge disabled) ll hh active select and activate row 1-6 l h l h read select column and start read burst 1-8 l h ll w rite select column and start new w rite burst 1-7 ll h l precharge 1-6 read ( w ith auto precharge) ll hh active select and activate row 1-6 l h l h read select column and start new read burst 1-7,10 l h ll w rite select column and start w rite burst 1-7,9,10 ll h l precharge 1-6 w rite ( w ith auto precharge) ll hh active select and activate row 1-6 l h l h read select column and start read burst 1-7,10 l h ll w rite select column and start new write burst 1-7,10 ll h l precharge 1-6 1. this table applies when ck e n-1 was h i gh and ck e nis h i gh (see truth table 2: clock e nable (ck e )andaftert x s n r/ t x srd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). e xcep- tions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. n o data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. w rite: a w rite burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with auto precharge e nabled: see note 10. w rite with auto precharge e nabled: see note 10. 4. a u to r e fr e s h and mode register set commands may only be issued when all banks are idle. 5. a b u rst t e rmi n at e command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or w rites listed in the command/action column include reads or w rites with auto precharge enabled and reads or w rites with auto precharge disabled. 8. requires appropriate dm masking. 9. a w rite command may be applied after the completion of data output. concurrent auto precharge: this device supports ?concurrent auto precharge?. w hen a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limita- tions apply (e.g. contention between r e ad data and w rit e data must be avoided). the mimimum delay from a read or write command with auto precharge enable, to a command to a different banks is summari z ed in table 5. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 48 of 77 2002-03-03 truth table 5: concurrent auto precharge from command to c o m m a n d (different bank) minimum delay with con- current auto precharge support u nits w rit e w/ap read or read w/ap 1 + (bl/2) + t w tr tck w rite ot w rite w/ap bl/2 tck precharge or activate 1 tck read w/ap read or read w/ap bl/2 tck w rite or w rite w/ap cl (rounded up) + bl/2 tck precharge or activate 1 tck hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 49 of 77 2002-03-03 simplified state diagram self auto idle mrs e mrs row precharge power w rite power act read a read r e fs r e fs x r e fa ck e l mrs ck eh ck eh ck e l w rite power applied automatic sequence command sequence read a w rite a read pr e pr e pr e pr e refresh refresh down power down active on a read a read a w rite a burst stop pr e all active precharge precharge pr e all read w rite pr e all = precharge all banks mrs = mode register set e mrs = e xtended mode register set r e fs = e nter self refresh r e fs x = e xitselfrefresh r e fa = auto refresh ck e l= e nter power down ck eh = e xit power down act = active w rite a = w rite with autoprecharge read a = read with autoprecharge pr e =precharge hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 50 of 77 2002-03-03 operating conditions absolute maximum ratings symbol parameter rating u nits v i n ,v o u t voltage on i/o pins relative to v ss ? 0.5tov ddq + 0.5 v v i n voltage on inputs relative to v ss ? 0.5 to + 3.6 v v dd voltageonv dd supply relative to v ss ? 0.5 to + 3.6 v v ddq voltageonv ddq supply relative to v ss ? 0.5 to + 3.6 v t a operating temperature (ambient) 0 to + 70 c t st g storage temperature (plastic) ? 55 to + 150 c p d power dissipation 1.5 w i o u t short circuit output current 50 ma note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not implied. e xposure to absolute maximum rating conditions for extended periods may affect reliability. input and output capacitances parameter symbol min. max. u nits n otes input capacitance: ck, ck c i1 2.0 3.0 pf 1 delta input capacitance c di1 -0.25pf1 input capacitance: all other input-only pins c i2 2.0 3.0 pf 1 input/output capacitance: dq, dqs, dm c io 4.0 5.0 pf 1, 2 delta input/output capacitance : dq, dqs, dm c dio -0.5pf1 1. these values are guaranteed by design and are tested on a sample base only. v ddq =v dd =2.5v 0.2v, f = 100m hz ,t a =25 c, v o u t (dc) = v ddq/2 ,vo u t (peak to peak) 0.2v. u nused pins are tied to ground 2. dm inputs are grouped with i/o pins reflecting the fact that they are matched in loading to dq and dqs to facilitate trace matching at the board level. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 51 of 77 electrical characteristics and dc operating conditions (0c t a 70 c; v d dq =2.5v 0.2v, v dd = + 2.5v 0.2v) symbol parameter min max u nits n otes v dd supply voltage 2.3 2.7 v 1 v ddq i/o supply voltage 2.3 2.7 v 1 v ss ,v ssq supply voltage, i/o supply voltage 0 0 v v r e f i/o reference voltage 0.49 x v ddq 0.51 x v ddq v1,2 v tt i/o termination voltage (system) v r e f ? 0.04 v r e f + 0.04 v 1, 3 v i h (dc) input h igh (logic1) voltage v r e f + 0.15 v ddq + 0.3 v 1 v il(dc) input low (logic0) voltage ? 0.3 v r e f ? 0.15 v 1 v i n (dc) input voltage level, ck and ck inputs ? 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.36 v ddq + 0.6 v 1, 4 vi ratio vi-matching pullup current to pulldown current 0.71 1.4 5 i i input leakage current any input 0v v i n v dd (all other pins not under test = 0v) ? 22 a1 i o z output leakage current (dqs are disabled; 0v v out v ddq ? 55 a1 i o h output h igh current, n ormal strength driver (v o u t = 1.95 v) ? 15.2 ma 1 i ol output low current, n ormal strength driver (v o u t = 0.35 v) 15.2 ma 1 1. inputs are not recogni z ed as valid until v r e f stabili z es. 2. v r e f is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on v r e f may not exceed 2 % of the dc value. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v r e f , and must track variations in the dc level of v r e f . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck . 5. the ration of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0v. for a given output, it rep- resents the maximum difference between pullup and pulldown drivers due to process variation. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 52 of 77 2002-03-03 normal strength pulldown and pullup characteristics 1. the nominal pulldown v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 2. the full variation in driver pulldown current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 3. the nominal pullup v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 4. the full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 5. the full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 6. the full variation in the ratio of the nominal pullup to pulldown current should be unity 10 % , for device drain to source voltages from 0.1 to 1.0v. normal strength pulldown characteristics normal strength pullup characteristics 0 0.5 1 1.5 2 2.5 0 20 40 60 80 100 120 140 1 o u t (ma) v ddq -v o u t (v) maximum n ominal h igh n ominal low minimum maximum n ominal h igh n ominal low minimum v ddq - v out (v) 0.5 1 1.5 2 2.5 0 0 -20 -40 -60 -80 -100 -120 -140 -160 i o u t (ma) hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 53 of 77 normal strength pulldown and pullup currents pulldown current (ma) pullup current (ma) voltage (v) n ominal low n ominal h igh min max n ominal low n ominal h igh min max 0.16.06.84.69.6 ? 6.1 ? 7.6 ? 4.6 ? 10.0 0.2 12.2 13.5 9.2 18.2 ? 12.2 ? 14.5 ? 9.2 ? 20.0 0.3 18.1 20.1 13.8 26.0 ? 18.1 ? 21.2 ? 13.8 ? 29.8 0.4 24.1 26.6 18.4 33.9 ? 24.0 ? 27.7 ? 18.4 ? 38.8 0.5 29.8 33.0 23.0 41.8 ? 29.8 ? 34.1 ? 23.0 ? 46.8 0.6 34.6 39.1 27.7 49.4 ? 34.3 ? 40.5 ? 27.7 ? 54.4 0.7 39.4 44.2 32.2 56.8 ? 38.1 ? 46.9 ? 32.2 ? 61.8 0.8 43.7 49.8 36.8 63.2 ? 41.1 ? 53.1 ? 36.0 ? 69.5 0.9 47.5 55.2 39.6 69.9 ? 43.8 ? 59.4 ? 38.2 ?77.3 1.0 51.3 60.3 42.6 76.3 ? 46.0 ? 65.5 ? 38.7 ? 85.2 1.1 54.1 65.2 44.8 82.5 ? 47.8 ? 71.6 ? 39.0 ? 93.0 1.2 56.2 69.9 46.2 88.3 ? 49.2 ? 77.6 ? 39.2 ? 100.6 1.3 57.9 74.2 47.1 93.8 ? 50.0 ? 83.6 ? 39.4 ? 108.1 1.4 59.3 78.4 47.4 99.1 ? 50.5 ? 89.7 ? 39.6 ? 115.5 1.5 60.1 82.3 47.7 103.8 ? 50.7 ? 95.5 ? 39.9 ? 123.0 1.6 60.5 85.9 48.0 108.4 ? 51.0 ? 101.3 ? 40.1 ? 130.4 1.7 61.0 89.1 48.4 112.1 ? 51.1 ? 107.1 ? 40.2 ? 136.7 1.8 61.5 92.2 48.9 115.9 ? 51.3 ? 112.4 ? 40.3 ? 144.2 1.9 62.0 95.3 49.1 119.6 ? 51.5 ? 118.7 ? 40.4 ? 150.5 2.0 62.5 97.2 49.4 123.3 ? 51.6 ? 124.0 ? 40.5 ? 156.9 2.1 62.9 99.1 49.6 126.5 ? 51.8 ? 129.3 ? 40.6 ? 163.2 2.2 63.3 100.9 49.8 129.5 ? 52.0 ? 134.6 ? 40.7 ? 169.6 2.3 63.8 101.9 49.9 132.4 ? 52.2 ? 139.9 ? 40.8 ? 176.0 2.4 64.1 102.8 50.0 135.0 ? 52.3 ? 145.2 ? 40.9 ? 181.3 2.5 64.6 103.8 50.2 137.3 ? 52.5 ? 150.5 ? 41.0 ? 187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2 pulldown and pullup process variations and conditions n ominal minimum maximum operating temperature 25 c0 c70 c v dd /v ddq 2.5v 2.3v 2.7v hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 54 of 77 2002-03-03 weak strength pulldown and pullup characteristics 1. the weak pulldown v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve 2. the weak pullup v-i curve for ddr sdram devices is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve. 3. the full variation in driver pullup current from minimum to maximum process, temperature, and voltage lie within the outer bounding lines of the v-i curve. 4. the full variation in the ratio of the maximum to minimum pullup and pulldown current does not exceed 1.7, for device drain to source voltages from 0.1 to 1.0. 5. the full variation in the ratio of the nominal pullup to pulldown current should be unity 10 % , for device drain to source voltages from 0.1 to 1.0v. weak strength pulldown characteristics weak strength pullup characteristics 0 10 20 30 40 50 60 70 80 0,0 0,5 1,0 1,5 2,0 2,5 vout [v] iout [ma] maxim um typical high typical low min im u m -80,0 -70,0 -60,0 -50,0 -40,0 -30,0 -20,0 -10,0 0,0 0,0 0,5 1,0 1,5 2,0 2,5 vout [v] iout [v] maximum typical high typical low minimum hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 55 of 77 weak strength driver pulldown and pullup characteristics pulldown current (ma) pullup current (ma) voltage (v) n ominal low n ominal h igh min max n ominal low n ominal h igh min max 0.1 3.4 3.8 2.6 5.0 -3.5 -4.3 -2.6 -5.0 0.2 6.9 7.6 5.2 9.9 -6.9 -8.2 -5.2 -9.9 0.3 10.3 11.4 7.8 14.6 -10.3 -12.0 -7.8 -14.6 0.4 13.6 15.1 10.4 19.2 -13.6 -15.7 -10.4 -19.2 0.5 16.9 18.7 13.0 23.6 -16.9 -19.3 -13.0 -23.6 0.6 19.6 22.1 15.7 28.0 -19.4 -22.9 -15.7 -28.0 0.7 22.3 25.0 18.2 32.2 -21.5 -26.5 -18.2 -32.2 0.8 24.7 28.2 20.8 35.8 -23.3 -30.1 -20.4 -35.8 0.9 26.9 31.3 22.4 39.5 -24.8 -33.6 -21.6 -39.5 1.0 29.0 34.1 24.1 43.2 -26.0 -37.1 -21.9 -43.2 1.1 30.6 36.9 25.4 46.7 -27.1 -40.3 -22.1 -46.7 1.2 31.8 39.5 26.2 50.0 -27.8 -43.1 -22.2 -50.0 1.3 32.8 42.0 26.6 53.1 -28.3 -45.8 -22.3 -53.1 1.4 33.5 44.4 26.8 56.1 -28.6 -48.4 -22.4 -56.1 1.5 34.0 46.6 27.0 58.7 -28.7 -50.7 -22.6 -58.7 1.6 34.3 48.6 27.2 61.4 -28.9 -52.9 -22.7 -61.4 1.7 34.5 50.5 27.4 63.5 -28.9 -55.0 -22.7 -63.5 1.8 34.8 52.2 27.7 65.6 -29.0 -56.8 -22.8 -65.6 1.9 35.1 53.9 27.8 67.7 -29.2 -58.7 -22.9 -67.7 2.0 35.4 55.0 28.0 69.8 -29.2 -60.0 -22.9 -69.8 2.1 35.6 56.1 28.1 71.6 -29.3 -61.2 -23.0 -71.6 2.2 35.8 57.1 28.2 73.3 -29.5 -62.4 -23.0 -73.3 2.3 36.1 57.7 28.3 74.9 -29.5 -63.1 -23.1 -74.9 2.4 36.3 58.2 28.3 76.4 -29.6 -63.8 -23.2 -76.4 2.5 36.5 58.7 28.4 77.7 -29.7 -64.4 -23.2 -77.7 2.6 36.7 59.2 28.5 78.8 -29.8 -65.1 -23.3 -78.8 2.7 36.8 59.6 28.6 79.7 -29.9 -65.8 -23.3 -79.7 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 56 of 77 2002-03-03 ac characteristics ( n otes 1-5 apply to the following tables; e lectrical characteristics and dc operating conditions, ac operating conditions, i dd specifications and conditions, and e lectrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. the figure below represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. system designers will use ibis or other simulation tools to correlate the timing ref- erence load to a system environment. manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. ac timing and i dd tests may use a v il to v i h swing of up to 1.5v in the test environment, but input timing is still refer- encedtov r e f (or to the crossing point for ck, ck ), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v i h (ac) . 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input lo w ( h i gh ) level) 6. for system characteristics like setup &h oldtime derating for slew rate, i/o delta rise/fall derating,ddr sdram slew rate standards, overshoot &u ndershoot specification and clamp v-i characteristics see the latest je d e c specification for ddr components ac output load circuit diagram / timing reference load ac operating conditions (0 c t a 70 c ; v ddq =2.5v 0.2v; v dd =2.5v 0.2v) symbol parameter/condition min max u nit n otes v i h (ac) input h igh (logic 1) voltage, dq, dqs, and dm signals v r e f + 0.31 v 1, 2 v il(ac) input low (logic 0) voltage, dq, dqs, and dm signals v r e f ? 0.31 v 1, 2 v id(ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v i x (ac) input closing point voltage, ck and ck inputs 0.5 * v ddq ? 0.2 0.5 * v ddq + 0.2 v 1, 2, 4 1. input slew rate = 1v/ns . 2. inputs are not recogni z ed as valid until v r e f stabili z es. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. the value of v i x is expected to equal 0.5 * v ddq of the transmitting device and must track variations in the dc level of the same. 50 ? timing reference point output (v o u t ) 30pf v tt hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 57 of 77 idd specification and conditions (0 c t a 70 c ; v ddq =2.5v 0.2v; v dd =2.5v symbol parameter/condition ddr200 ddr266a ddr333 u nit n otes typ. max typ. max typ. max 4) i dd0 operating current : one bank; active / precharge; t rc =t rc mi n ;t ck = t ck mi n ; dq, dm, and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 125 160 135 170 155 200 ma 1, 2 i dd1 operating current : one bank; active / read / precharge; burst = 4; refer to the following page for detailed test conditions. 135 170 145 180 170 215 ma 1, 2 i dd2p precharge power-down standby current : all banks idle; power- down mode; ck e v il ma x ;t ck =t ck mi n 8 1210141218ma1,2 i dd2f precharge floating standby current :cs v i h mi n , all banks idle; ck e v i h mi n ;t ck =t ck mi n ,address and other control inputs chang- ingonceperclockcycle,v i n =v r e f for dq, dqs and dm. 30 40 40 50 45 60 ma 1, 2 i dd2q precharge quiet standby current :cs v i h mi n , all banks idle; ck e v i h mi n ;t ck =t ck mi n ,address and other control inputs stable at v i h mi n or v il ma x ;v i n =v r e f for dq, dqs and dm. 18 25 20 28 30 40 ma 1, 2 i dd3p active power-down standby current : one bank active; power- down mode; ck e v il ma x ;t ck =t ck mi n ;v i n =v r e f for dq, dqs and dm. 11 16 14 18 17 23 ma 1, 2 i dd3 n active standby current : one bank active; active / precharge;cs v i h mi n ;ck e v i h mi n ;t rc =t ras ma x ;t ck =t ck mi n ;dq,dm,and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 40 50 55 70 60 75 ma 1, 2 i dd4r operating current: one bank active; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs outputs changing twice per clock cycle; cl = 2 for ddr200, and ddr266a, cl=3 for ddr333; t ck =t ck mi n ;i o u t =0ma 135 165 165 200 200 245 ma 1, 2 i dd4 w operating current : one bank active; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changing twice per clock cycle; cl = 2 for ddr200, and ddr266a, cl=3 for ddr333; t ck =t ck mi n 130 160 160 195 190 235 ma 1, 2 i dd5 auto-refresh current :t rc =t rfc mi n , distributed refresh 235 290 255 310 270 335 ma 1, 2 i dd6 self-refresh current :ck e 0.2v; external clock on; t ck =t ck mi n standard version 2.5 5 2.5 5 2,5 5 ma 1, 2, 3 low power version tbd. tbd. tbd. tbd. tbd. tbd. ma i dd7 operating current: four bank; four bank interleaving with bl=4; refer to the following page for detailed test conditions. 285 350 315 380 330 405 ma 1, 2 1. i dd specifications are tested after the device is properly initiali z ed and measured at 100 m hz for ddr200, 133 m hz for ddr266 and 166 m hz for ddr333 2. input slew rate = 1v/ns . 3. e nables on-chip refresh and address counters 4. test condition for typical values : v dd =2.5v,ta=25 o c, test condition for maximum values: test limit at v dd =2.7v,ta=10 o c hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 58 of 77 2002-03-03 idd current measurement conditions idd1 : operating current : one bank operation 1. only one bank is accessed with t rc(min) , burst mode, address and control inputs on n op edge are changing once per clock cycle. l out =0ma 2. timing patterns - ddr200 (100mh z , cl=2) : tck = 10 ns, cl=2, bl=4, trcd = 2 * tck, tras = 5 * tck setup: a0 n r0 nn p0 n read : a0 n r0 nn p0 n - repeat the same timing with random address changing 50 % of data changing at every burst - ddr266a (133mh z , cl=2) : tck = 7.5 ns, cl=2, bl=4, trcd = 3 * tck, trc = 9 * tck, tras = 5 * tck setup: a0 nn r0 n p0 nnn read : a0 nn r0 n p0 nnn - repeat the same timing with random address changing 50 % of data changing at every burst - ddr333 (166mh z , cl=2.5) : tck = 6 ns, cl=2.5, bl=4, trcd = 3 * tck, trc = 9 * tck, tras = 5 * tck setup: a0 nn r0 n p0 nnn read : a0 nn r0 n p0 nnn - repeat the same timing with random address changing 50 % of data changing at every burst 3.legend : a=activate, r=read, w = w rite, p=precharge, n = n op idd7 : operating current: four bank operation 1. four banks are being interleaved with t rc(min) , burst mode, address and control inputs on n op edge are not changing. l out =0ma 2. timing patterns - ddr200 (100mh z , cl=2) : tck = 10 ns, cl=2, bl=4, trrd = 2 * tck, trcd= 3 * tck, read with autoprecharge setup: a0 n a1 r0 a2 r1 a3 r2 read : a0 r3 a1 r0 a2 r1 a3 r2- repeat the same timing with random address changing 50 % of data changing at every burst - ddr266a (133mh z , cl=2) : tck = 7.5 ns, cl=2, bl=4, trrd = 2 * tck, trcd = 3 * tck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read : a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50 % of data changing at every burst - ddr333 (166mh z , cl=2.5) : tck = 6 ns, cl=2.5, bl=4, trrd = 2 * tck, trcd = 3 * tck setup: a0 n a1 r0 a2 r1 a3 r2 n r3 read : a0 n a1 r0 a2 r1 a3 r2 n r3 - repeat the same timing with random address changing 50 % of data changing at every burst 3.legend : a=activate, r=read, w = w rite, p=precharge, n = n op hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 59 of 77 electrical characteristics & ac timing - absolute specifications (0 c t a 70 c ; v ddq =2.5v 0.2v; v dd =2.5v 0.2v) (part 1 of 2) symbol parameter ddr200 -8 ddr266a -7 ddr333 -6 u nit n otes min max min max min max t ac dq output access time from ck/ck ? 0.8 + 0.8 ? 0.75 + 0.75 ? 0.7 + 0.7 ns 1-4 t dqsck dqs output access time from ck/ck ? 0.8 + 0.8 ? 0.75 + 0.75 ? 0.6 + 0.6 ns 1-4 t c h ck high-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1-4 t cl ck low-level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1-4 t h p clock h alf period min (t cl ,t c h )min(t cl ,t c h )min(t cl ,t c h )ns1-4 t ck clock cycle time cl=3.0 812712612ns1-4 t ck cl=2.5 812712612ns1-4 t ck cl = 2.0 10 12 7.5 12 7.5 12 ns 1-4 t d h dq and dm input hold time 0.6 0.5 0.45 ns 1-4 t ds dq and dm input setup time 0.6 0.5 0.45 ns 1-4 t ip w control and addr. input pulse width (each input) 2.5 2.2 2.2 ns 1-4,10 t dip w dq and dm input pulse width (each input) 2.0 1.75 1.75 ns 1-4,10 t hz data-out high-impedence time from ck/ck ? 0.8 + 0.8 ? 0.75 + 0.75 ? 0.7 + 0.7 ns 1-4, 5 t l z data-out low-impedence time from ck/ck ? 0.8 + 0.8 ? 0.75 + 0.75 ? 0.7 + 0.7 ns 1-4, 5 t dqss w rite command to 1st dqs latching transition 0.75 1.25 0.75 1.25 0.75 1.25 t ck 1-4 t dqsq dqs-dq skew (dqs & associated dq signals) tsop66 + 0.6 + 0.5 + 0.45 ns 1-4 t q h s data hold skew factor tsop66 1.0 0.75 0.55 ns 1-4 t q h dq/dqs output hold time t h p -t q h s t h p -t q h s t h p -t q h sns 1-4 t dqsl, h dqs input low (high) pulse width (write cycle) 0.35 0.35 0.35 t ck 1-4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 0.2 t ck 1-4 t ds h dqs falling edge hold time from ck (write cycle) 0.2 0.2 0.2 t ck 1-4 t mrd mode register set command cycle time 2 2 2 t ck 1-4 t w pr e s w rite preamble setup time 0 0 0 ns 1-4, 7 t w pst w rite postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1-4, 6 t w pr e w rite preamble 0.25 0.25 0.25 t ck 1-4 t is address and control input setup time fast slew rate 1.1 0.9 0.75 ns 2-4, 10,11 slow slew rate 1.1 1.0 0.8 ns t i h address and control input hold time fast slew rate 1.1 0.9 0.75 ns slow slew rate 1.1 1.0 0.8 ns t rpr e read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck 1-4 t rpst read postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1-4 hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 60 of 77 2002-03-03 t ras active to precharge command 50 120,000 45 120,000 42 70,000 ns 1-4 t rc active to active/auto-refresh command period 70 65 60 ns 1-4 t rfc auto-refresh to active/auto-refresh command period 80 75 72 ns 1-4 t rcd active to read or w ritedelay 202018ns1-4 t rp precharge command period 20 20 18 ns 1-4 t rap active to autoprecharge delay 20 20 18 ns 1-4 t rrd active bank a to active bank b command 15 15 12 ns 1-4 t w r w rite recovery time 15 15 15 ns 1-4 t dal auto precharge write recovery + precharge time (twr/tck) + (trp/tck) t ck 1-4,9 t w tr internal write to read command delay 1 1 1 t ck 1-4 t x s n r e xit self-refresh to non-read command 80 75 75 ns 1-4 t x srd e xit self-refresh to read command 200 200 200 t ck 1-4 t r e fi average periodic refresh interval 7.8 7.8 7.8 s1-4,8 1. input slew rate > = 1v/ns for ddr333 & ddr266 and = 1v/ns for ddr200 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck ,isv r e f. ck/ck slew rate are > =1.0v/ns. 3. inputs are not recogni z ed as valid until v r e f stabili z es. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics ( n ote 3) is v tt . 5. t hz and t l z transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a spe- cific voltage level, but specify when the device is no longer driving ( hz ), or begins driving (l z ). 6. the maximum limit for this parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid ( h i gh ,lo w , or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. w hen no writes were previously in progress on the bus, dqs will be transitioning from h i- z to logic lo w . if a previous write was in progress, dqs could be h i gh , lo w , or transitioning from h i gh to lo w at this time, depending on t dqss . 8. a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 9. for each of the terms, if not already an integer, round to the next highest integer. tck is equal to the actual system clock cycle time. 10. these parameters guarantee device timing, but they are not necessarily tested on each device 11. fast slew rate > =1.0v/ns,slowslewrate > =0.5v/nsand < 1v/ns for command/address and ck & ck slew rate > 1.0 v/ns, mea- sured between vo h (ac) and vol(ac) electrical characteristics & ac timing - absolute specifications (0 c t a 70 c ; v ddq =2.5v 0.2v; v dd =2.5v 0.2v) (part 2 of 2) symbol parameter ddr200 -8 ddr266a -7 ddr333 -6 u nit n otes min max min max min max hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 61 of 77 electrical characteristics & ac timing for ddr266a - applicable specifications expressed in clock cycles (0 c t a 70 c ; v ddq =2.5v 0.2v; v dd =2.5v 0.2v) symbol parameter ddr266a @ cl=2 u nits n otes min max t mrd mode register set command cycle time 2 t ck 1-5 t w pr e w rite preamble 0.25 t ck 1-5 t ras active to precharge command 6 16000 t ck 1-5 t rc active to active/auto-refresh command period 9 t ck 1-5 t rfc auto-refresh to active/auto-refresh command period 10 t ck 1-5 t rcd active to read or w rite delay 3 t ck 1-5 t rp precharge command period 3 t ck 1-5 t rrd active bank a to active bank b command 2 t ck 1-5 t w r w rite recovery time 2 t ck 1-5 t dal auto precharge write recovery + precharge time 5 t ck 1-5 t w tr internalwritetoreadcommanddelay 1 t ck 1-5 t x s n r e xit self-refresh to non-read command 10 t ck 1-5 t x srd e xit self-refresh to read command 200 t ck 1-5 1. input slew rate = 1v/ns 2. the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck ,isv r e f. 3. inputs are not recogni z ed as valid until v r e f stabili z es. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics ( n ote 3) is v tt . 5. t hz and t l z transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a spe- cific voltage level, but specify when the device is no longer driving ( hz ), or begins driving (l z ). hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 62 of 77 2002-03-03 timing diagrams data input (write) (timing burst length = 4) data output (read) (timing burst length = 4) t d h t ds t d h t ds t dqsl di n = data in for column n. 3 subsequent elements of data in are applied in programmed order following di n. di n dqs dq dm don?t care t dqs h t q h (data output hold time from dqs) t dqsq and t q h are only shown once and are shown referenced to different edges of dqs, only for clarify of illustration. . dqs dq t dqsq max t q h t dqsq and t q h both apply to each of the four relevant edges of dqs. t dqsq max. is used to determine the worst case setup time for controller data capture. t q h is used to determine the worst case hold time for controller data capture. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 63 of 77 initialize and mode register sets t i h 200 s t is t i h t is t i h t is t i h t is t i h t is t i h t is t i h t is t mrd t rfc t rfc t rp t mrd t mrd t cl t ck t c h t vtd pr ee mrs mrs pr e ar ar mrs n op act cod e cod e cod e ra cod e cod e cod e ra ba0=l ba0=l ba h igh- z h igh- z power-up: vdd and ck stable e xtended mode register set load mode register, reset dll load mode register (witha8=l) vdd vddq vtt (system * ) vr e f ck ck e command dm a0-a9, a11 a10 ba0, ba1 dqs dq lvcmos lo w l e v e l all ba n ks ba0= h ba1=l ba1=l ba1=l all ba n ks * vtt is not applied directly to the device, however t vtd must be ** t mrd is required before any command can be applied and the two autorefresh commands may be moved to follow the first mrs, greater than or equal to z ero to avoid device latchup. 200 cycles of ck are required before a read command can be applied. but precede the second precharge all command. don?t care 200 cycles of ck ** ck hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 64 of 77 2002-03-03 power down mode t i h t is t i h t is t is t is t i h t is t cl t c h t ck n op valid valid * valid valid e nter power down mode e xit power down mode n o column accesses are allowed to be in progress at the time power down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power down mode shown is precharge power down. if this command is an active (or if at least one row is already active), then the power down mode shown is active power down. ck e command addr dqs dq dm don?t care ck ck n op hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 65 of 77 auto refresh mode t i h t is t i h t is t i h t is t rfc t rp t cl t c h t ck pr en op n op ar n op ar n op n op n op ra ra ba pr e = precharge; act = active; ra = row address; ba = bank address; ar = autorefresh. n op commands are shown for ease of illustration; other valid commands may be possible at these times. dm, dq, and dqs signals are all don ' t care/high- z for operations shown. valid valid act ra ck e command a0-a8 a9, a11,a12 a10 ba0, ba1 dqs dq dm ba n k(s) don?t care all ba n ks o ne ba n k t rfc ck ck hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 66 of 77 2002-03-03 self refresh mode 200 cycles t i h t is t x srd, t x sr n t i h t is t is t is t i h t is t rp * t ck t cl t c h ar valid n op valid e nter self refresh mode e xit self refresh mode n op * = device must be in the all banks idle state before entering self refresh mode. ** =t x s n r is required before any non-read command can be applied, and t x srd (200 cycles of ck). ck e command addr dqs dq dm don?t care are required before a read command can be applied. ck ck clock must be stable before exiting self refresh mode hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 67 of 77 read without auto precharge (burst length = 4) t hz (max) t l z (max) t hz (min) t rpst t l z (min) t i h t is t i h t is t i h t is t i h t is t i h t i h t is t rp t cl t c h t ck pr en op n op act n op n op n op n op do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. * =don ' tcareifa10is h igh at this point. pr e = precharge; act = active; ra = row address; ba = bank address. n op commands are shown for ease of illustration; other commands may be valid at these times. ba x ba x valid valid valid n op read col n ra ra ba x * do n ck e command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 all ba n ks o ne ba n k t dqsck (max) t rpr e cl=2 t rpr e don?t care case 1: t ac /t dqsck =min case 2: t ac /t dqsck =max t rpst t ac (max) t l z (max) t dqsck (min) t ac (min) do n ck ck dis ap dis ap = disable auto precharge. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 68 of 77 2002-03-03 read with auto precharge (burst length = 4) t hz (max) t l z (max) t hz (min) t rpst t l z (min) t i h t is t i h t is t i h t is t i h t is t i h t i h t is t rp t cl t c h t ck n op n op n op act n op n op n op n op do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. en ap = enable auto precharge. act = active; ra = row address. n op commands are shown for ease of illustration; other commands may be valid at these times. ba x valid valid valid n op read col n ra ra do n ck e command a10 ba0, ba1 dm dqs dq dqs dq a0-a9, a11, a12 t dqsck (max) t rpr e cl=2 t rpr e don?t care case 1: t ac /t dqsck =min case 2: t ac /t dqsck =max t rpst t ac (max) t l z (max) t dqsck (min) t ac (min) do n en ap ba x ck ck t hz (min) hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 69 of 77 bank read access (burst length = 4) t hz (max) t l z (max) t hz (min) t rpst t l z (min) t i h t is t i h t is t i h t is t i h t is t i h t is t cl t c h t ck read n op pr en op n op act n op n op ba x ba x * valid n op act ra ra ba x do n ck ck ck e command a10 ba0, ba1 dm dqs dq dqs dq t dqsck (max) t rpr e cl=2 cl=2 t rpr e don?t care case 1: t ac /t dqsck =min case 2: t ac /t dqsck =max t rpst t ac (max) t l z (max) t dqsck (min) t ac (min) do n col n ra ra all ba n ks ra o ne ba n k dis ap ba x t rp do n = data out from column n. 3 subsequent elements of data out are provided in the programmed order following do n. dis ap = disable auto precharge. * =don ' tcareifa10is h igh at this point. pr e = precharge; act = active; ra = row address; ba = bank address. n op commands are shown for ease of illustration; other commands may be valid at these times. t rcd a0-a9, a11, a12 t ras t rc t l z (min) hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 70 of 77 2002-03-03 write without auto precharge (burst length = 4) t i h t w pst t dqsl t i h t is t i h t is t i h t is t i h t is t i h t is t rp t cl t c h t ck n op n op n op pr en op n op act n op ba x ba n op w rite col n ra ra ba x * valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. dis ap = disable auto precharge. * =don ' tcareifa10is h igh at this point. pr e = precharge; act = active; ra = row address; ba = bank address. n op commands are shown for ease of illustration; other valid commands may be possible at these times. din ck ck ck e command a10 ba0, ba1 dqs dq dm dis ap all ba n ks o ne ba n k t w r t w pr e s t dqs h don?t care a0-a9, a11, a12 t dqss =min. t dqss t w pr e t ds h hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 71 of 77 write with auto precharge (burst length = 4) n op commands are shown for ease of illustration; other valid commands may be possible at these times. act = active; ra = row address; ba = bank address. t i h t w pst t dqsl t i h t is t i h t is t i h t is t i h t is t is t rp t cl t c h t ck n op n op n op n op n op n op act n op ba x ba n op w rite col n ra ra valid din = data in for column n. 3 subsequent elements of data in are applied in the programmed order following din. en ap = e nable auto precharge. ck ck ck e command a10 ba0, ba1 dqs dq dm t w r t dqss t w pr e s t dqs h don?t care valid valid en ap a0-a9, a11, a12 t dal t dqss =min. t ds h t w pr e din hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 72 of 77 2002-03-03 bank write access (burst length = 4) t w pst t dqsl t i h t is t i h t is t i h t is t i h t is t i h t is t cl t c h t ck t ras w rite n op n op n op n op pr en op n op ba x n op act ra ra di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n. dis ap = disable auto precharge. * = don ' tcareifa10is h igh at this point. pr e =precharge;act=active;ra=rowaddress. n op commands are shown for ease of illustration; other valid commands may be possible at these times. din valid ba x ck e command a10 ba0, ba1 dqs dq dm ck ck t w pr e s t w r t rcd all ba n ks o ne ba n k dis ap don?t care a0-a9, a11, a12 col n ba x t dqss t dqs h t ds h t w pr e t dqss =min. hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 73 of 77 write dm operation (burst length = 4) t i h t w pst t dqsl t i h t is t i h t is t is t rp t cl t c h t ck n op n op n op pr en op n op act n op n op w rite col n ra din ck ck ck e command a10 ba0, ba1 dqs dq dm t w r t dqss don?t care valid t i h t is t i h t is ba x ba ra ba x * all ba n ks o ne ba n k dis ap di n = data in for column n. 3 subsequent elements of data in are applied in the programmed order following di n (the second element of the 4 is masked). dis ap = disable auto precharge. * =don ' tcareifa10is h igh at this point. pr e = precharge; act = active; ra = row address; ba = bank address. n op commands are shown for ease of illustration; other valid commands may be possible at these times. a0-a9, a11, a12 t dqs h t ds h t dqss =min. t w pr e s hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram page 74 of 77 2002-03-03 package dimensions plastic package, p-tsopii-66 (400mil; 66 lead ) tsop66 0,65 basic 0,3 0,08 0,805 r e f 0,05 min 1,20 max 22,22 0,13 lead # 1 10,16 0,13 0,5 0,1 11,76 0,2 0.1 0,25 basic g auge plane seating plane hyb25d512400/800/160at(l)/ac(l) 512-mbit double data rate sdram 2002-03-17 page 75 of 77 table of content features 1 description 1 pin configuration tsop66 2 input/output functional description 3 ordering information 4 block diagram (128mbit x 4) 5 block diagram (64mbit x 8) 6 block diagram (32mbit x 16) 7 functional description 8 initiali z ation 8 register definition 9 mode register operation 10 burst definition 11 operating mode 12 required cas latencies 12 e xtended mode register 13 e xtended mode register definition 14 commands 15 deselect, n o operation ( n op) 15 mode register set 15 active 15 read 15 w rite 15 precharge 15 auto precharge 16 burst terminate 16 auto refresh 16 self refresh 16 truth table 1a: commands 17 truth table 1b: dm operation 17 operations 18 bank/row activation 18 read command 20 read burst: cas latencies 21 consecutive read bursts 22 n on-consecutive read bursts 23 random read accesses 24 terminating a read burst 26 read to w rite 27 read to precharge 28 w rite command 29 w rite burst 31 w rite to w rite 32 w rite to w rite: max dqss, n on-consecutive 33 random w rite cycles 34 w rite to read: n on-interrupting 35 hyb25d512400/800/160at(l) 512-mbit double data rata sdram preliminary datasheet 2002-03-17 2002-03-17 page 76 of 77 w rite to read: interrupting 36 w rite to read: minimum dqss, interrupting 37 w rite to read: n ominal dqss, interrupting 38 w rite to precharge: n on-interrupting 39 w rite to precharge: interrupting 40 w rite to precharge: minimum dqss 41 w rite to precharge: n ominal dqss 42 precharge 43 precharge command 43 power-down 44 truth table 2: clock e nable (ck e )45 truth table 3: current state (same bank) 46 truth table 4: current state (different bank) 47 truth table 5: concurrent auto precharge 48 simplified state diagram 50 operating conditions 51 absolute maximum ratings 51 input and output capacitances 51 dc e lectrical operating conditions 52 n ormal strength characteristics 53 w eak strength characteristics 55 ac characteristics 57 ac output load circuit diagram 57 ac operating conditions 57 idd specification and conditions 58 idd current measurement conditions 59 e lectrical characteristics & ac timing 60 timing diagrams 63 data input ( w rite) 63 data output (read) 63 initiali z e and mode register sets 64 power down mode 65 auto refresh mode 66 self refresh mode 67 read without auto precharge (bl = 4) 68 read with auto precharge (bl = 4) 69 bank read access (burst length = 4) 70 w rite without auto precharge (bl = 4) 71 w rite with auto precharge (burst length = 4) 72 bank w rite access (burst length = 4) 73 w rite dm operation (burst length = 4) 74 package dimensions 75 table of content 76 attention please ! hyb25d512400/800/160at(l) 512-mbit double data rata sdram preliminary datasheet 2002-03-17 2002-03-17 page 77 of 77 as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. this information describes the type of components and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact i n fi ne o n technologies offices in munich or the i n fi ne o n technologies sales offices and representatives worldwide. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest i n fi ne o n technologies office or representative. packing please use the recycling operators known to you. w e can help you - get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. y ou must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of i n fi ne o n technologies, may only be used in life- support devices or systems 2 with the express written approval of i n fi ne o n technologies. 1. a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life- support device or system, or to affect the safety or effectiveness of that device or system. 2. life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered. |
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